code generation - x86 instruction encoding tables -

I'm in the middle of rewriting your assembler this I am curious about applying the disassembly I simplify it And want to make compact, and there are concepts I can exploit while doing this.

The x86 instruction from opcode (probably prefix bytes are also required, one bit) is possible to determine the rest of the encoding. I know that many people have written tables to do this.

I am not interested in sleeping, but instruction encoding, because it is a real difficult problem for each opcode number I should know:

• Is this Moderram in instruction?
• How quickly does this command?
• Is encoding an immediate use?
• Is there an instruction in the field in the indicator-related address immediately?
• What kind of registrar uses modem for operators and register fields?

sandpile.org I wanted something very much, but it's in a format that is not easy to parse.

Before writing and validating the table before I decided, to write this question, do you know about these tables which are present anywhere? In a form that does not require much effort to parse.

  b byte w words v word or dword (or Qword), operating size depends on attribute (0x66) z word or dword or DWORD), operand size attribute J instruction-relative address Depending on the type (the next character type describes), the instruction instruction group, the modrm area (the opera type describing the next character) is the R modrm area (the next two letters are the description of the register and operability type), but the modrum indicates the field Should do memory Ratyksh defined offset (described next character is described) F FPU t separate table, but there is no argument x 0 1 2 3 4 5 6 7 8 9 Abiseediif 0 Arbibi Arvivi Arbibi Arvivi Bees Arbibi Arvivi RBB RVV BZ T 1 RBB RVV Lord Ravi BZ Lord Ravi Lord Ravi BZ 2 RBB RVV RBB RVV BZ RBB RVV RBB RVV BZ 3 RBB RVV RBB RVV BZ RBB RVV RBB RVV BZ 4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6 _ _ MVV z Rvvz b Rvvb 7 JB JB JB JB JB JB JB JB JB JB JB JB JB JB JB JB 8 GBB Gvz GBB GVB RBB RVV RBB RVV RBB RVV RBB RVV MVV 9 _ _ _ _ _ _ _ _ _ _ _ _ _ Ob ov ob ov _ _ _ _ _ bz _ _ _ _ _ _ bbbbbbbbvvvvvvv c GBB gvb w _ _ _ _ _ _ _gb gv. GB G.V. FFFFFFFFE JZ JZ JB F _ _ GB G.V. _ _ _ _ _ _ _ _ GB G.V.  

Here I've got a table format happens for the first operand table can be written directly out from the text file would contain I directives related to Siaissi division Has left.

For two-byte instructions, I need four types of tables. For three-byte instructions, I will need more than two tables. For the FPU instructions, 8 tables are required, which are fortunately very easy, after that I had a large portion of the x86 instructions covered. Although I am just fine with one or two tables.

Further, some instruction groups may need some small arrays to identify the instruction type.

I believe that what you want can be. This is a list of x86-64 commands in XML format, which should be easy to parse.